Influence of Si SBD P+ ring junction depth on ESD robustness

As the device size gets smaller and smaller, electrostatic discharge (ESD) has become an important factor affecting the reliability of semiconductor devices. For a Schottky barrier diode (SBD), the P⁺ ring junction depth has significant impact on ESD robustness. Based on this, the model of a 1A-series SBD chip is established using SILVACO TCAD software in this paper, the ESD failure mechanism and the impact of junction pushing time on P⁺ ring junction depth, especially on ESD robustness is also investigated by adding HBM mode pulse to anode. The results indicate that the SBD works well when the ESD test level is below 8 kV but failures at the test level of 8 kV because of the over current-induced heat failure; Besides, when time increases from 80 min to 160 min with the increment of 20 min, the junction depth also increases from 1.245 μm to 1.752 μm, at the same time, the current density becomes smaller and the capability of P⁺ ring sharing electric field with Schottky barrier also gets strengthened respectively, SBD can get HBM-mode ESD robustness range from 5 kV to 20 kV, which means increasing of the junction depth can significantly enhance the HBM ESD robustness of the diode.