Sub-100 μm2 PNP load cell for sub-ns/25 kbit ECL RAM

The potential of sub-100 μm² PNP load cells for sub-ns/256 kb ECL (emitter coupled logic) RAM have been studied. Soft-error immunity and write switching operation are investigated with several kinds of cell structures. By using a novel cell structure with a p⁺ overlap diffusion layer in the p^- substrate of the cell area, the collected charge in the collector node of the memory cell, which is responsible for soft-error in circuit operation, was reduced by 30% in comparison to the conventional structure. To evaluate cell soft-error immunity, a novel method of cell storage charge calculation taking account of diffusion capacitances is proposed. For high-seed write switching operation, by utilizing the novel trench isolation structure which is partially inserted into the active region of the memory cell, a 50% decrease in the minimum write pulse width compared with the conventional structure was simulated. By using the optimized 86 μm² PNP load cell, which has the two novel cell structures mentioned above, a simulated address access time of 0.8 ns was achieved for a 256 kbit ECL RAM