A 13.56 Mbps PSK receiver for very high data rate 13.56MHz smart card and NFC applications

In order to increase the data rate of 13.56MHz inductively coupled systems, such as contactless smartcards, e-Passports and near field communication devices (NFC) devices, a multi-level Phase Shift Keying (PSK) modulation was proposed to the ISO standardization body. The challenge of increasing the data rate within the same power budget led to the design of a low-power analog/mixed signal 16PSK demodulator, as well as a digital signal processing hardware IP that estimates and equalizes the channel. The total measured current consumption of the analog front end in 140nm CMOS is less than 100μA, with an area of 0.07mm². The digital IP current and area estimation in 140nm CMOS are respectively 750μA and 0.24mm². The evaluated system demonstrates a bit error rate (BER) of 10^-6 for data rates up to 10.17 Mbps and a BER of 10^-5 for 13.56 Mbps. A Hamming coding scheme is utilized to achieve frame error rates below 2%.