An analytical surface potential and threshold voltage model of fully depleted strained-SOI MOSFETs in nanoscale with high-k gate oxide

To meet high performance (HP) and low power (LP) circuit requirements, increased channel mobility is required to boost the transistor drive current and/or reduce Vdd for lower power dissipation without performance penalty. Strain and more advanced engineered substrates developed on the SOI platform provide solutions for technology nodes of 32 nm and beyond. A study on the performance with two-dimensional analytical model of single layer fully depleted strained-silicon-on-insulator MOSFET is described. We investigate: 1) the surface potential; 2) the Threshold voltage of the device. The results show that this structure can suppress the short channel effects (SCEs) and improve the sub threshold performance in Nanoelectronics application. The model is verified by numerical simulation.