Generation of optimal universal logic modules

The realization of efficient universal logic modules (ULMs) is a challenging topic in circuit design. The goal is to find a representation that allows to realize as many Boolean functions as possible by permutation of inputs or phase assignment. In this paper an exact algorithm for finding a minimal circuit for a ULM is presented. The approach is parametrisized in several ways, e.g. the user can define a library of gates and specify the functions that should be realized within the module. Starting from an input description that enumerates all functions to be realized the algorithm generates an area and/or delay minimal netlist. Experimental results are given to show the efficiency of the approach