DocumentCode
345107
Title
The X-MatchLITE FPGA-based data compressor
Author
Nùñez, José Luis ; Feregrino, Claudia ; Bateman, Stephen ; Jones, Simon
Author_Institution
Electron. Syst. Design Group, Loughborough Univ. of Technol., UK
Volume
1
fYear
1999
fDate
1999
Firstpage
126
Abstract
This paper introduces a hardware amenable algorithm for lossless data compression and a highly integrable architecture which enables Gbit/s compression using contemporary ASIC technology. An FPGA prototype of the architecture is presented. A comparison between this prototype and the full version of the system is made together with the details of the engineering decisions needed to successfully realize an ASIC compressor in FPGA technology
Keywords
computer architecture; content-addressable storage; data compression; field programmable gate arrays; ASIC technology; X-MatchLITE FPGA-based data compressor; engineering decisions; hardware amenable algorithm; highly integrable architecture; lossless data compression; Application specific integrated circuits; Data compression; Design engineering; Dictionaries; Field programmable gate arrays; Hardware; Image coding; Prototypes; Signal processing; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
EUROMICRO Conference, 1999. Proceedings. 25th
Conference_Location
Milan
ISSN
1089-6503
Print_ISBN
0-7695-0321-7
Type
conf
DOI
10.1109/EURMIC.1999.794458
Filename
794458
Link To Document