DocumentCode :
345108
Title :
Implementing a quantitative model for the `effective´ signal processing in the auditory system on a dedicated digital VLSI hardware
Author :
Schwarz, A. ; Mertsching, B. ; Brucke, M. ; Nebel, W. ; Tschorz, J. ; Kollmeier, B.
Author_Institution :
Dept. of Comput. Sci., Hamburg Univ., Germany
Volume :
1
fYear :
1999
fDate :
1999
Firstpage :
133
Abstract :
A digital VLSI implementation of an algorithm modeling the `effective´ signal processing of the human auditory system is presented. The model consists of several stages psychoacoustically and physiologically motivated by the signal processing in the human ear and was successfully applied to various speech processing applications. The processing scheme was partitioned for implementation in a set of three chips. Due to local properties of the signal dynamic and the necessary arithmetical precision different approaches for number representation and appropriate arithmetic operators were investigated and implemented. It is demonstrated how an application of the model has been used to determine the necessary wordlengths for a transfer of the algorithm into a version suitable for hardware implementation. Fix point arithmetic is used in the linear parts of the origin algorithm and a special small floating point operator set was developed for the nonlinear part. This part was coded in behavioral VHDL and synthesized with Synopsys Behavioral Compiler. The hardware algorithm is being evaluated on different implementation levels for a FPGA and will be manufactured as ASICs in a later version. The presented FPGA chip set will be combined with a commercial DSP system (TMS320C6201) for real time and reconfigurable signal processing
Keywords :
VLSI; application specific integrated circuits; audio signal processing; digital signal processing chips; field programmable gate arrays; fixed point arithmetic; hardware description languages; DSP system; FPGA; Synopsys Behavioral Compiler; TMS320C6201; auditory system; behavioral VHDL; dedicated digital VLSI hardware; fix point arithmetic; floating point operator set; hardware algorithm; number representation; quantitative model; reconfigurable signal processing; signal dynamic; signal processing; speech processing; Auditory system; Digital signal processing chips; Field programmable gate arrays; Hardware; Humans; Partitioning algorithms; Psychoacoustic models; Psychology; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
EUROMICRO Conference, 1999. Proceedings. 25th
Conference_Location :
Milan
ISSN :
1089-6503
Print_ISBN :
0-7695-0321-7
Type :
conf
DOI :
10.1109/EURMIC.1999.794459
Filename :
794459
Link To Document :
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