DocumentCode
345139
Title
An optimization of simulation time in the hardware accelerated VLSI simulator
Author
Kucharski, Grzegorz ; Wrona, Wlodzimierz
Author_Institution
PTK Centerel, Katowice, Poland
Volume
1
fYear
1999
fDate
1999
Firstpage
410
Abstract
In this paper we present some aspects of time optimization in hardware accelerated simulator of VLSI integrated circuits. The acceleration of simulation is achieved thanks to special data format of driver, which is used at the most time consuming operations of a simulator, e.g. finding transaction with least delay time, active signal and driver updating etc
Keywords
VLSI; circuit optimisation; field programmable gate arrays; hardware description languages; logic design; active signal; driver updating; hardware accelerated VLSI simulator; least delay time; optimization; simulation time; time optimization; Acceleration; Circuit simulation; Communication system control; Electrical capacitance tomography; Field programmable gate arrays; Hardware design languages; Integrated circuit modeling; Signal processing; Signal resolution; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
EUROMICRO Conference, 1999. Proceedings. 25th
Conference_Location
Milan
ISSN
1089-6503
Print_ISBN
0-7695-0321-7
Type
conf
DOI
10.1109/EURMIC.1999.794502
Filename
794502
Link To Document