The techniques of fixed pattern noise reduction for high speed digital CMOS image sensor

Techniques of fixed pattern noise reduction for CMOS image sensor are presented. Double sampling reusing the existing switch-capacitor amplifier of column ADC, double resets for 5-T active pixel, and negative offset storage of the cyclic ADC, are proposed to reduce the fixed pattern noise caused by the threshold voltage´s mismatch of the amplifying and transmitting transistor of the pixel, and the offset of the amplifier in ADC, respectively. Experimental results show that the typical offset voltages observed are 0.97mV, which is about 1LSB, that indicate that these techniques are efficient without additional processes and devices.