A fourth-order, low-pass, MASH ΔΣ modulator with CBSC technique in 0.18μm CMOS

In this paper a new gain stage for comparator-based switched-capacitor circuits (CBSC) is presented. In contrast with the conventional structure the proposed structure utilizes an extra comparator to make a variable comparator threshold, in order to attenuating the overshoot at the end of the coarse phase. To verify the idea, we designed a 2-1-1 cascaded Multi- stage (MASH) ΔΣ modulator, based on the proposed architecture in a 0.18-μm 1P6M standard CMOS process. It achieves 76-dB signal-to noise-and-distortion ratio (SNDR) and 78-dB dynamic range (DR) at input 132.81 KHz. In addition it consumes 3.65mW from a 1.8-V power supply at 32MS/s (OSR=16).