Title :
How can we overcome both side channel analysis and fault attacks on RSA-CRT?
Author :
Kim, Chong Hee ; Quisquater, Jean-Jacques
Author_Institution :
Univ. Catholique de Louvain, Louvain-la-Neuve
Abstract :
RSA cryptosystem is one of the most widely used algorithms nowadays. However when it is implemented in embedded devices such as smart cards, it can be vulnerable to power analysis attacks and fault attacks. To defeat all known side channel attacks and fault attacks, several countermeasures should be used together. However due to the low computation capability of the embedded devices, we have to find the best solution or combination among countermeasures. Furthermore, we should be careful since a countermeasure may produce another new vulnerability such as Yen et. al.´s safe-error attack in a simple power analysis (SPA) countermeasure. In 2005, Giraud proposed a scheme secure against simple power analysis as well as fault attack (FA). Afterwards, Fumaroli and Vigilant proposed an exponentiation algorithm secure against differential power analysis (DPA) as well as simple power analysis and fault attack with almost 1.5 times increase in time complexity compared to Giraud´s. To the authors´ best knowledge, it was a first trial to prevent SPA, DPA, and FA simultaneously on exponentiation with one solution. In this paper we show Fumaroli and Vigilant´s scheme can be broken by fault attacks and propose a direction to construct efficient countermeasures secure against all known side channel analyses and fault attacks on RSA-CRT with low time complexity.
Keywords :
computational complexity; public key cryptography; Chinese remainder theorem; RSA cryptosystem; RSA-CRT; differential power analysis; exponentiation algorithm; fault attack; side channel analysis; simple power analysis; time complexity; Algorithm design and analysis; Cryptography; Electromagnetic analysis; Electromagnetic fields; Embedded computing; Energy consumption; Fault diagnosis; Information analysis; Smart cards; X-ray lasers;
Conference_Titel :
Fault Diagnosis and Tolerance in Cryptography, 2007. FDTC 2007. Workshop on
Conference_Location :
Vienna
Print_ISBN :
978-0-7695-2982-0
DOI :
10.1109/FDTC.2007.11