Analytical optimization of Si and Si-Ge epitaxial base transistors for very high speed ECL gates

Author

Ghannam, Moustafa Y.

Author_Institution

Interuniv. Microelectron. Center, IMEC, Leuven, Belgium

fYear

1991

fDate

9-10 Sep 1991

Firstpage

166

Lastpage

169

Abstract

Simple analytical expressions for the ECL (emitter coupled logic) gate delays are proposed and applied to typical ECL gates using Si and SiGe epitaxial base bipolar transistors, and their accuracy is demonstrated. By studying some of the tradeoffs existing between some of the parameters, it is shown how such a simple analysis can be helpful for adjusting the parameters of the transistors to the optimum values, rather than systematically having to push the technology to the limit

Keywords

Ge-Si alloys; bipolar integrated circuits; emitter-coupled logic; heterojunction bipolar transistors; integrated logic circuits; optimisation; semiconductor device models; semiconductor epitaxial layers; Si; SiGe; SiGe epitaxial base bipolar transistors; analytical expressions; device physics; emitter coupled logic; gate delays; semiconductors; tradeoffs; very high speed ECL gates; Bipolar transistor circuits; Bipolar transistors; Cutoff frequency; Degradation; Delay; Doping; Germanium silicon alloys; Microelectronics; Narrowband; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1991., Proceedings of the 1991

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-0103-X

Type

conf

DOI

10.1109/BIPOL.1991.160980

Filename

160980