A 500 V 1A 1-chip inverter IC with a new electric field reduction structure

Author

Endo, Koichi ; Baba, Yoshiro ; Udo, Yuso ; Yasui, Mitsuru ; Sano, Yoshiyuki

Author_Institution

MicroElectron. Center, Toshiba Corp., Kawasaki, Japan

fYear

1994

fDate

31 May-3 Jun 1994

Firstpage

379

Lastpage

383

Abstract

A 500 V 1 A three-phase inverter IC has been developed by using a new electric field reduction structure SRFP (Scroll shaped Resistive-Field-Plate). This HV-IC process is a BiCMOS process with a dielectric isolated (DI) wafer. Si wafer direct bonding (SDB) technique is applied to the DI wafer. Output devices are lateral IGBTs with high-speed collector structures. Without SIPOS, an SRFP has the same field reduction effect and the same electric shield effect as a SIPOS-RFP. In this report, we show that turn off time of IGBT depends on N⁺ pattern in the collector and existence of P⁺ layer around the DI area. High-speed (280 nsec) and low saturation (2.8 V) voltage IGBTs are realized by using optimization of collector pattern

Keywords

insulated gate bipolar transistors; 1 A; 2.8 V; 280 ns; 500 V; BiCMOS process; HVIC process; N⁺ pattern; P⁺ layer; Si; Si wafer direct bonding; dielectric isolated wafer; electric field reduction structure; high-speed collector structures; lateral IGBTs; scroll shaped resistive-field-plate; single-chip inverter; three-phase inverter IC; Capacitors; Coupling circuits; Electric breakdown; Insulated gate bipolar transistors; Inverters; Leakage current; Low voltage; Resistors; Voltage control; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1994. ISPSD '94., Proceedings of the 6th International Symposium on

Conference_Location

Davos

ISSN

1063-6854

Print_ISBN

0-7803-1494-8

Type

conf

DOI

10.1109/ISPSD.1994.583792

Filename

583792