Mapping the AWE-RLC model into a simple RC circuit with its application to buffer insertion

Author

Abdullah, A.R. ; Kabbani, Ammar ; Raahemifar, Kaamran

Author_Institution

Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada

fYear

2011

fDate

8-11 May 2011

Abstract

GAM, TPN and AWE methods have been accepted by many researchers as methods of modeling on chip interconnects as RC, and RLC circuits. In this paper a platform to generate the T and Π configurations for RC, RLC and RLCG models based on GAM, TPN and AWE methods is proposed. With the Π configuration of AWE based RLC model provides the best performance, this model has been mapped to an equivalent simple RC model. This improved RC model has been utilized for buffer insertion, which caused interconnect delay to be reduced and the number of buffers and their sizes to be lowered.

Keywords

RC circuits; RLC circuits; equivalent circuits; integrated circuit interconnections; two-port networks; Π configuration; AWE-RLC model; T configuration; asymptotic waveform evaluation; buffer insertion; equivalent simple RC model; global approximation method; interconnect delay; two-port network; Accuracy; Delay; Integrated circuit interconnections; Integrated circuit modeling; Load modeling; Mathematical model; RLC circuits; buffer insertion; on-chip interconnect; segmentation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering (CCECE), 2011 24th Canadian Conference on

Conference_Location

Niagara Falls, ON

ISSN

0840-7789

Print_ISBN

978-1-4244-9788-1

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2011.6030428

Filename

6030428