Title :
Flexible simulation and modeling for 2D topology NoC system design
Author :
Gharan, Masoud Oveis ; Khan, Gul N.
Author_Institution :
Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada
Abstract :
Network on Chip (NoC) is a new paradigm that can solve the problems related to System on Chip (SoC) design. These problems and challenges become more significant when the complexity of SoC increases. The vast volume of these challenges requires a new and flexible NoC test framework (simulator) to be investigated. We have developed a general purpose SystemC based NoC simulator that employs some new approaches to have a superior test system as compared to the past NoC simulators. The simulator mainly target 2D regular NoC topologies where deterministic and adaptive routing techniques that play a key role in the NoC performance. Various NoC design parameters are analyzed by trading off throughputs and latencies. The results show that for some cases the new Line-Probe routing is faster and contention free for local traffic in Torus topology.
Keywords :
circuit simulation; flexible electronics; integrated circuit design; network routing; network topology; network-on-chip; 2D topology NOC system design; NoC design parameters; SoC design; Torus topology; adaptive routing technique; deterministic routing technique; flexible NoC modeling; flexible NoC simulation; flexible NoC test framework; general purpose SystemC; line-probe routing; network on chip; system on chip; Generators; Network topology; Routing; System-on-a-chip; Throughput; Topology; Traffic control; NoC Simulation and Modeling; On-chip Routing Methods; SoC Design;
Conference_Titel :
Electrical and Computer Engineering (CCECE), 2011 24th Canadian Conference on
Conference_Location :
Niagara Falls, ON
Print_ISBN :
978-1-4244-9788-1
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2011.6030434
