Title :
An optimal formulation for test scheduling network-on-chip using multiple clock rates
Author :
Salamy, Hassan ; Harmanani, Haidar M.
Author_Institution :
Ingram Sch. of Eng., Texas State Univ., San Marcos, TX, USA
Abstract :
With the growing trend of increasing number of cores on a single chip, bus-based communication is suffering from bandwidth and scalability issues. As a result, the new approach is to use a network on chip (NoC) as the main communication system on a SoC. NoC provides the flexibility and scalability much needed in the era of multi-cores. NoC-based systems also provide the capability of multiple clocking that is widely used in many SoC nowadays. In this paper, an optimal integer linear programming (ILP) solution for test scheduling of cores in a NoC-based SoC using multiple clock rates is presented. Results on different benchmarks show the effectiveness of our techniques.
Keywords :
integer programming; integrated circuit reliability; integrated circuit testing; linear programming; network-on-chip; NoC-based SoC; bandwidth issues; bus-based communication; multicores; multiple clock rates; optimal integer linear programming solution; scalability issues; system-on-a-chip; test scheduling network-on-chip; Benchmark testing; Clocks; Equations; Mathematical model; Scheduling; System-on-a-chip;
Conference_Titel :
Electrical and Computer Engineering (CCECE), 2011 24th Canadian Conference on
Conference_Location :
Niagara Falls, ON
Print_ISBN :
978-1-4244-9788-1
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2011.6030441