Physical aware low power clock gates synthesis algorithm for high speed VLSI design

In this paper, a new clock tree distribution design flow and algorithm of clock gates splitting to improve the clock tree power dissipation had been presented. The clock gating components are inserted in clock tree during VLSI design flow to reduce clock tree dynamic power consumption. The effective splitting and physical placement of the clock gates are vital to ensure the clock gating efficiency. The paper presents an approach that is able to achieve optimum power saving on clock tree during full operation mode and shut off mode.