An FPGA implementation of 3-D signal transmission system

A 3-dimensinal (3-D) signal transmission system is implemented on field programmable gate array (FPGA) in this paper. We exploit 3-D 8-ary and 32-ary signal constellations to map input binary data, and Gram-Schmidt orthogonalization procedure (GSOP) to generate transmitted signals. The prototypes of function modules such as encoder and demapper are implemented by means of Verilog hardware description language (VHDL). The modules are synthesized and emulated using FPGA tools. Emulation based on the fixed-point format demonstrates that the system has almost the same symbol error rate (SER) as a software test-bed. Hence, it is considered that the implemented system operates correctly.