Title :
A reconfigurable RTOS with HW/SW co-scheduling for SOPC
Author :
Deng, Qingxu ; Wei, Shuisheng ; Xu, Hai ; Han, Yu ; Yu, Ge
Author_Institution :
Dept. of Comput. Sci. & Eng., Northeastern Univ., Boston, MA, USA
Abstract :
Emerging reconfigurable hardware, SOPC (system on programmable Chip), requires a RTOS to reuse the abundant source code. This paper presents a RTOS with the ability to co-schedule HW/SW, and discusses its architecture in detail for SOPC. The paper addresses an efficient run-time partitioning algorithm for block partitioning of FPGA. At last, a case study will be presented to validate our approach. The RTOS can decreases NRE costs and facilitates integrating hardware and software seamlessly.
Keywords :
electronic engineering computing; field programmable gate arrays; hardware-software codesign; operating systems (computers); real-time systems; reconfigurable architectures; scheduling; system-on-chip; FPGA; HW/SW coscheduling; block partitioning; reconfigurable RTOS; reconfigurable hardware; run-time partitioning algorithm; source code; system on programmable chip; Application software; Computer architecture; Embedded software; Field programmable gate arrays; Hardware; Operating systems; Partitioning algorithms; Resource management; Runtime; System-on-a-chip;
Conference_Titel :
Embedded Software and Systems, 2005. Second International Conference on
Print_ISBN :
0-7695-2512-1
DOI :
10.1109/ICESS.2005.9
