Title :
Effect of Poly-Si Gate Depletion on Tuning Range in MOS Varactors
Author :
Kulkarni, Jaydeep P. ; Bhat, Navakanta
Author_Institution :
ECE Department, Purdue University, West Lafayette, Indiana, USA. Phone: 765-494-9448, Email: jaydeep@purdue.edu
Keywords :
CMOS process; CMOS technology; Capacitance; Diodes; Doping; Electrodes; Implants; MOS devices; Q factor; Varactors;
Conference_Titel :
Device Research Conference, 2006 64th
Conference_Location :
State College, PA, USA
Print_ISBN :
0-7803-9748-7
DOI :
10.1109/DRC.2006.305128
