A Generic Multi-Modulus Divider Architecture for Fractional-N Frequency Synthesisers

This paper describes the design of a new technique and architecture of multi-modulus divider for Sigma-Delta fractional-N PLL frequency synthesisers. The proposed architecture uses a memory-controlled technique that can achieve a wider range of prescaler modulus values, more flexible operation, and lower power dissipation. It has been implemented in an FPGA in conjunction the store-sequence architecture and a range of Sigma-Delta modulators. Both simulated and measured results are shown to demonstrate that a substantial improvement in performance is possible.