Overcoming the Mixed Signal Chip Simulation Limits of the EF Anti-Jitter Circuit

The EF-AJC is a mixed signal circuit operating with GHz sawtooth waveforms and feedback time constants of a few milliseconds. Jitter has to be modeled to sub-picosecond accuracy. Conventional time-step simulation is impossible in reasonable time. The paper addresses the validity of the ´indirect´ simulation methods that have to be used. The ´simulations´ are compared with 500 MHz results from a Fujitsu micro-electronics test chip. This 90 nm chip suppresses jitter by 8 times. The estimated residual jitter is less than an estimated 2 to 5 ps.