DocumentCode
3453503
Title
Asynchronous reconfigurable computing array design
Author
Zhang, Jiale ; Pan, Xuezeng ; Shen, Haibin
Author_Institution
Coll. of Comput. Sci. & Technol., Zhejiang Univ., Hangzhou, China
fYear
2005
fDate
16-18 Dec. 2005
Abstract
We present a novel architecture of asynchronous reconfigurable computing array (ARCA) to seek the balance between performance and versatility. Advancing the completion detector of control circuit, a modified structure of asynchronous micropipeline based on DSDCVSL is discussed. The analysis and simulation of our ARCA have both resulted in high-performance and low-power consumption, and it can be used as an IP module integrated into a system on chip to built the reconfigurable computing platform.
Keywords
asynchronous circuits; logic design; reconfigurable architectures; system-on-chip; DSDCVSL; IP module; asynchronous micropipeline; asynchronous reconfigurable computing array design; control circuit; system-on-chip; Circuits; Clocks; Computational modeling; Computer architecture; Computer science; Educational institutions; Logic devices; Neural networks; Reconfigurable logic; Telecommunication computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Software and Systems, 2005. Second International Conference on
Print_ISBN
0-7695-2512-1
Type
conf
DOI
10.1109/ICESS.2005.33
Filename
1609888
Link To Document