Title :
Low voltage low power high-speed BiCMOS multiplier
Author :
Cheng, Kuo-Hsing ; Yeha, Yu-Kwang ; Farn-Sou Lian
Author_Institution :
Dept. of Electr. Eng., TamKang Univ., Taipei, Taiwan
Abstract :
A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth´s algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation
Keywords :
BiCMOS logic circuits; digital arithmetic; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; multiplying circuits; parallel processing; 1 micron; 16 bit; 2.5 V; 298 muW; 32.74 ns; Booth algorithm; LV BiCMOS multiplier; advanced arithmetic architecture; high-speed multiplier; low power BiCMOS multiplier; low voltage multiplier; modified array scheme; parallel multiplier; Arithmetic; BiCMOS integrated circuits; CMOS technology; Delay; Digital audio players; Feedback circuits; Inverters; Low voltage; Power dissipation; Space technology;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.814820
