Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster

Author

Dhia, A.B. ; Naviner, Lirida ; Matherat, Philippe

Author_Institution

Inst. TELECOM, TELECOM ParisTech, Paris, France

fYear

2012

fDate

27-29 June 2012

Firstpage

31

Lastpage

36

Abstract

This paper proposes a method to analyze the effect of manufacturing defects and soft errors: stuck-ats and bit flips, on a cluster in a Mesh FPGA architecture. The cluster reliability is evaluated with a technique that is used in case of either a single error or multiple simultaneous faults. Simulation results show that the cluster is more robust to stuck-ats than to bit-flips, whatever the configuration memory is. Then, for selective hardening against bit flips, we propose an approach to identify the critical path and the most eligible component that is likely to improve the cluster reliability.

Keywords

SRAM chips; field programmable gate arrays; integrated circuit reliability; pattern clustering; SRAM-based FPGA cluster; bit flips; cluster reliability; configuration memory; manufacturing defects; mesh FPGA architecture; multiple simultaneous faults; selective hardening; single error; soft errors; stuck-ats; Field programmable gate arrays; Integrated circuit reliability; Joining processes; Multiplexing; Table lookup; Cluster; Crossbar; FPGA architecture; Interconnect; Look-up Table (LUT); Rent parameter; SPR analysis; bit flip; eligibility; fault tolerance; selective hardening; stuck-at;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International

Conference_Location

Sitges

Print_ISBN

978-1-4673-2082-5

Type

conf

DOI

10.1109/IOLTS.2012.6313837

Filename

6313837