FASTBUS simulation tools

A generalized model of a FASTBUS master is presented. It is used with simulation tools to aid in the specification, design, and production of FASTBUS slave modules and provides a mechanism to interact with the electrical schematics and software models to predict performance. The model is written in the IEEE Std 1076-1987 hardware description language VHDL. A model of the ancillary timing controller (ATC) logic is also presented. VHDL was chosen to provide portability to various platforms and simulation tools. The models, in conjunction with most commercially available simulators, will perform all of the transactions specified in IEEE Std 960-1989. The models may be used to study the behavior of electrical schematics and other software models and detect violations of the FASTBUS protocol. The master model accepts a stream of high-level commands from an ASCII file to initiate FASTBUS transactions. Using this standard-base command language to direct the model of the master, hardware engineers can simulate FASTBUS transactions in the language used by physicists and programmers to operate FASTBUS systems.<>