Title :
A real-case application of a synergetic design-flow-oriented SER analysis
Author :
Vilchis, Miguel ; Venkatraman, Ramnath ; Costenaro, Enrico ; Alexandrescu, Dan
Author_Institution :
LSI Corp., Milpitas, CA, USA
Abstract :
We present a methodology that investigates SEEs in complex SOCs. The analysis integrates tightly with the design flow and provides static and dynamic de-rating algorithms. This approach is in good agreement with alpha testing results obtained from a 40nm CMOS testchip with sixty-four independently controlled/selectable Advanced Encryption Standard (AES) based processing element (PE) blocks.
Keywords :
CMOS integrated circuits; cryptography; integrated circuit design; radiation hardening (electronics); system-on-chip; AES based processing element blocks; CMOS test chip; PE block; SoC; dynamic derating algorithms; independently controlled-selectable advanced encryption standard; size 40 nm; soft error rate; static derating algorithms; synergetic design-flow-oriented SER analysis; Circuit faults; Clocks; Flip-flops; Registers; Single event upset; Standards; Testing; Single Event Effects; Single Event Transient; Single Event Upset; Soft Error Rate;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International
Conference_Location :
Sitges
Print_ISBN :
978-1-4673-2082-5
DOI :
10.1109/IOLTS.2012.6313839
