Leakage power reduction in low-voltage CMOS designs

Lowering supply voltage is one of the most effective ways of reducing power dissipation. Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between the leakage current and the transistor threshold voltage in the weak inversion region, static current (and hence, static power power dissipation) can no longer be ignored. In this paper the author presents different design techniques such as multiple threshold voltage, dynamic threshold control, substrate biasing, and leakage control using transistor stacking to achieve large improvements in leakage power during both stand-by and active mode of operation