Design a hardware network firewall on FPGA

Catastrophe events can happen when a computer or a computer network is exposed to the Internet without any security protection. The security issues can be mitigated by setting up a firewall between the inside network and the outside world. This paper describes a design of a highly customizable hardware packet filtering firewall to be embedded on a network gateway. A packet filtering firewall controls the header field in each network data packet based on its configuration and permits or denies the data passing through the network. An Altera FPGA platform is used for implementing and evaluating the hardware network firewall. The hardware design provides much faster speed compared to traditional software applications.