Characterization of leakage power in CMOS technologies

A model to statistically characterize the leakage power of CMOS digital circuits is presented. Based on the subthreshold leakage characterization at transistor and cell level, the leakage power consumption of a standard cell circuit is obtained. Also, in order to estimate the leakage power variability for a fixed state, a model of variations due to process is introduced. Using these models, the P_LEAK distribution is found to be asymmetric around the nominal value showing a long tail for high consuming circuits. The model has been found effective in evaluating the correlation of leakage power with other performance specs, in particular delay. We have shown that an IC with short L, and therefore, with high P_LEAK will be faster than nominal ones and an IC with long L, and therefore, with low P_LEAK will be slower. Predicted results are consistent with available experimental data