Signal through-silicon via planning in 3D fixed-outline floorplanning

In this paper, we will study fixed-outline floorplanning in 3D-IC. Although there is abundant literature on 3D-IC floorplanning, none of them consider the areas and positions of signal through-silicon vias (TSVs). In previous research, TSVs are viewed as points during the floorplanning stage. Ignoring the areas, positions and connections of TSVs, previous research plans TSVs dispersively and estimates the wirelength by measuring the bounding box of pins in a net only. Moreover, although thermal issue is critical, there is a trade-off between wirelength and maximum temperature. Aggressively reducing the temperature may sacrifice the wirelength and impact the performance. Therefore, in this paper, we will propose a 3D floorplaning algorithm which simultaneously plans hard macros and TSV-blocks to minimize the wirelength and the maximum on-chip temperature. Experimental results show that our algorithm achieves high successful rate. Compared to the average wirelength of a post-processing TSV planning algorithm, our result is shorter by 22.3%. In addition, we also compare our algorithm to a 3D fixed-outline floorplanner without considering thermal issue. The result shows that, our algorithm effectively reduces the maximum on-chip temperature by 45% at the expense of 3.9% increase in wirelength.