DocumentCode
3454629
Title
A time-predictable stack cache
Author
Abbaspour, Sahar ; Brandner, F. ; Schoeberl, Martin
Author_Institution
Dept. of Appl. Math. & Comput. Sci., Tech. Univ. of Denmark, Lyngby, Denmark
fYear
2013
fDate
19-21 June 2013
Firstpage
1
Lastpage
8
Abstract
Real-time systems need time-predictable architectures to support static worst-case execution time (WCET) analysis. One architectural feature, the data cache, is hard to analyze when different data areas (e.g., heap allocated and stack allocated data) share the same cache. This sharing leads to less precise results of the cache analysis part of the WCET analysis. Splitting the data cache for different data areas enables composable data cache analysis. The WCET analysis tool can analyze the accesses to these different data areas independently. In this paper we present the design and implementation of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache. The combination of stack cache instructions and the hardware implementation of the stack cache is a further step towards time-predictable architectures.
Keywords
cache storage; program compilers; program diagnostics; LLVM C++ compiler; WCET analysis; cache sharing; data cache analysis; real-time systems; stack cache instructions; stack cache management; time-predictable architecture; time-predictable stack cache; worst-case execution time; Computer architecture; Hardware; Pipelines; Reduced instruction set computing; Registers; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), 2013 IEEE 16th International Symposium on
Conference_Location
Paderborn
Type
conf
DOI
10.1109/ISORC.2013.6913225
Filename
6913225
Link To Document