Architecting energy efficient crossbar-based memristive random-access memories

Memristive devices are promising candidates for future high-density, power-efficient memories. The sneak path problem of purely-resistive crossbars and the inherent nanowire voltage drop, however, prevent the use of memristors in large-scale memory systems. In this paper we provide a simple yet flexible 3D memory organization and decoding scheme for memristive crossbars that exploits the benefits of the CMOL interface and avoid the limitations of conventional resistive crossbars. We propose an electrical model of the system to simulate and estimate its delay and energy consumption and show that such memories provide high read/write concurrency with power consumption per read/write operation that is significantly lower than that of DRAM.