DocumentCode
3454854
Title
Event-driven on-line co-simulation with fault diagnostic
Author
Baklashov, Mikhail
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
2012
fDate
27-29 June 2012
Firstpage
123
Lastpage
126
Abstract
This paper introduces a functional co-validation technique realized inside co-simulation methodology, environment and tool. On-line co-simulation intends to concurrently simulate an execution of original binary applications and their binary translated images. Both, original and translated instructions execute under an Instruction Set Simulator (ISS) in a Virtual System Prototyping Environment (VSPE) that models hardware platform or chipset targeted to a given Instruction Set Architecture (ISA). Real world applications accounting for billions of instructions executing in VSPE under Operating System (OS) control may exhibit hard to reproduce and debug fatal failures. When dealing with such enormous state space, co-validation becomes a critical factor under tight schedules of the software/hardware co-design. The paper presents a mathematical model that allows for abstracting the huge co-simulated state space and special events of interest. A fault diagnostic mode implemented inside the tool couples run time software exception handling mechanisms with the events thus accommodating application runs to runtime failures for further debugging guidance. The tool implemented in C++ runs seamlessly inside VSPE.
Keywords
C++ language; discrete event simulation; exception handling; hardware-software codesign; instruction sets; operating systems (computers); program debugging; software prototyping; system recovery; C++ implementation; ISA; ISS; OS control; VSPE; binary application execution; binary translated images; chipset; cosimulated state space abstraction; critical factor; event-driven online cosimulation; fatal failure debugging; fault diagnostic mode; functional covalidation technique; hardware platform; instruction set architecture; instruction set simulator; mathematical model; operating system control; run-time software exception handling mechanisms; runtime failures; simulation tool; software-hardware codesign; translated instructions; virtual system prototyping environment; Computational modeling; Context; Hardware; Mathematical model; Registers; Software; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International
Conference_Location
Sitges
Print_ISBN
978-1-4673-2082-5
Type
conf
DOI
10.1109/IOLTS.2012.6313854
Filename
6313854
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