DocumentCode :
3454916
Title :
Task Scheduling for Dynamic SMP Clusters with Communication on the Fly for Bounded Number of Resources
Author :
Masko, Lukasz
Author_Institution :
Inst. of Comput. Sci., Polish Acad. of Sci., Warsaw
fYear :
2005
fDate :
4-6 July 2005
Firstpage :
13
Lastpage :
20
Abstract :
The paper presents an algorithm for scheduling parallel tasks in a parallel architecture based on multiple dynamic SMP clusters. Processors can be switched between shared memory modules in the runtime. Memory modules and processors are organized in computational system on chip modules of a fixed size and are inter-connected by a local communication network implemented in a network-on-chip technology (NoC). Processors located in the same SoC module can share their data and communicate using a technique of data transfers on the fly. A number of such SoC modules can be connected using a global interconnection network to form a larger infrastructure. The presented algorithm schedules initial macro dataflow program graph for such an architecture with a given number of SoC modules, considering a fixed size of a module. First, it distributes program graph nodes among processors, assuming no distribution between SoC modules. Then it transforms and schedules computations and communications to use processor switching and read on the fly facilities. Finally, using genetic algorithm, it divides the whole set of processors into subsets of a given size, which then are mapped to separate SoC modules
Keywords :
data flow graphs; genetic algorithms; network-on-chip; parallel architectures; parallel programming; processor scheduling; shared memory systems; workstation clusters; NoC; SoC; computational system on chip modules; data transfers on the fly; genetic algorithm; global interconnection network; macro dataflow program graph; multiple dynamic SMP clusters; network-on-chip; parallel architecture; parallel task scheduling; processor switching; shared memory modules; Clustering algorithms; Communication switching; Computer networks; Dynamic scheduling; Network-on-a-chip; Parallel architectures; Processor scheduling; Runtime; Scheduling algorithm; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Computing, 2005. ISPDC 2005. The 4th International Symposium on
Conference_Location :
Lille
Print_ISBN :
0-7695-2434-6
Type :
conf
DOI :
10.1109/ISPDC.2005.45
Filename :
1609948
Link To Document :
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