DocumentCode
3454935
Title
Computation-in-memory based parallel adder
Author
Hoang Anh Du Nguyen ; Lei Xie ; Taouil, Mottaqiallah ; Nane, Razvan ; Hamdioui, Said ; Bertels, Koen
Author_Institution
Lab. of Comput. Eng., Delft Univ. of Technol., Delft, Netherlands
fYear
2015
fDate
8-10 July 2015
Firstpage
57
Lastpage
62
Abstract
Today´s computing systems suffer from memory/communication bottleneck, resulting in energy and performance inefficiency. This makes them incapable to solve data-intensive applications within economically acceptable limits. Computation-In-Memory (CIM) architecture, based on the integration of storage and computation in the same physical location using non-volatile memristor technology offers a potential solution for the memory bottleneck. This paper presents a CIM based parallel adder, and shows its potentials and superiority for intensive computing and massive parallelism by comparing it with state-of-the art computing systems including multicore, GPU and FPGA architecture. The results show that CIM based parallel adder can achieve at least two orders of magnitude improvement in computational efficiency, energy efficiency and area efficiency.
Keywords
adders; logic design; memory architecture; memristors; FPGA architecture; GPU architecture; computation-in-memory based parallel adder; data-intensive applications; memory bottleneck; memory/communication bottleneck; multicore architecture; nonvolatile memristor technology; Adders; Computer integrated manufacturing; Delays; Field programmable gate arrays; Graphics processing units; Multicore processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanoscale Architectures (NANOARCH), 2015 IEEE/ACM International Symposium on
Conference_Location
Boston, MA
Type
conf
DOI
10.1109/NANOARCH.2015.7180587
Filename
7180587
Link To Document