DocumentCode :
3455056
Title :
A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology
Author :
Yoon, Jae-Man ; Lee, Kangyoon ; Park, Seung-Bae ; Kim, Seong-Goo ; Seo, Hyoung-Won ; Son, Young-Woong ; Kim, Bong-Soo ; Chung, Hyun-Woo ; Lee, Choong-Ho ; Lee, Won-Sok ; Kim, Dong-Chan ; Park, Donggun ; Lee, Wonshik ; Ryu, Byung-Il
Author_Institution :
Semiconductor R&D Division, Samsung Electronics Co., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do, 449-711, Korea. Tel) 82-31-209-4741, Fax) 82-31-209-3274, E-mail) jaeman.yoon@samsung.com
fYear :
2006
fDate :
26-28 June 2006
Firstpage :
259
Lastpage :
260
Keywords :
Doping; Etching; Impact ionization; Investments; Ion implantation; Leakage current; Random access memory; Research and development; Silicon compounds; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Device Research Conference, 2006 64th
Conference_Location :
State College, PA, USA
ISSN :
1548-3770
Print_ISBN :
0-7803-9748-7
Type :
conf
DOI :
10.1109/DRC.2006.305083
Filename :
4097627
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3455056
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