DocumentCode
3455092
Title
A Low-Cost Strained Silicon SRAM Technology with Reduced Contact Resistance
Author
Polishchuk, Igor ; Levy, Sagy ; Kapre, Ravindra ; Pohland, Oliver ; Ramkumar, Krishnaswamy ; Shah, Nirav ; Thompson, Scott E.
Author_Institution
Cypress Semiconductor, 198 Champion Court, San Jose, CA 95134 USA. phone: (408)545 7149, email: ixp@cypress.com
fYear
2006
fDate
26-28 June 2006
Firstpage
263
Lastpage
264
Abstract
This paper presents a simple and cost-effective method to enhance 65nm SRAM technology performance using a single stress liner, resulting in 25% increase in cell read current. A novel slot contact process allows significant improvement of NMOS drive current without PMOS degradation, by relaxing the undesirable strain in the PMOS. This new slot process also results in significant reduction of the S/D contact resistance.
Keywords
CMOS logic circuits; CMOS technology; Capacitive sensors; Compressive stress; Contact resistance; MOS devices; Random access memory; Silicon; Substrates; Tensile stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference, 2006 64th
Conference_Location
State College, PA, USA
ISSN
1548-3770
Print_ISBN
0-7803-9748-7
Type
conf
DOI
10.1109/DRC.2006.305174
Filename
4097629
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