DocumentCode :
3455196
Title :
Charge Trapping WN Nano-dots with /or without Nitride Sub-layer for FinFET FLASH Memory
Author :
Choe, Jeong-Dong ; Lee, Jong Jin ; Ahn, Young Joon ; Lee, Se-Hoon ; Choi, Byung Yong ; Sung, Suk Kang ; Cho, Eun Suk ; Kim, Seung Beom ; Cheong, Seong Hwee ; Lee, Choong-Ho ; Chung, Ilsub ; Park, Kyuncharn ; Park, Donggun ; Ryu, Byung-Il
Author_Institution :
Device Research Team, Samsung Electronics Co., Yongin-City, Kyungki-Do, KOREA; School of Information and Communication Engineering, Sungkyunkwan University, Kyungki-Do, KOREA. Phone: 82-31-209-6162, Fax: 82-31-209-9861, E-mail: ivo.choe@samsung.com
fYear :
2006
fDate :
26-28 June 2006
Firstpage :
273
Lastpage :
274
Keywords :
Annealing; Degradation; FinFETs; Flash memory; Nanocrystals; Nanoscale devices; Nonvolatile memory; Silicon compounds; Threshold voltage; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Device Research Conference, 2006 64th
Conference_Location :
State College, PA, USA
ISSN :
1548-3770
Print_ISBN :
0-7803-9748-7
Type :
conf
DOI :
10.1109/DRC.2006.305179
Filename :
4097634
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3455196
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