Title :
Design of a D-PHY chip for mobile display interface supporting MIPI standard
Author :
Kim, Beom-Dae ; Lee, Sang-Jin ; Kim, Doo-Hwan ; Cho, Kyoungrok
Abstract :
This paper presents a D-PHY chip design for MIPI (Mobile Industry Processor Interface) standard. The MIPI is a flexible, source-synchronous serial interface standard connecting a host processor to a display and camera modules as used in mobile devices. The D-PHY consists of LP (low-power) mode block, HS (high-speed) mode block and control blocks. We implemented D-PHY chip using 0.13-um CMOS process under 1.2V supply. As a result, HS mode shows 1Gbps with jitter 5% and 0.74mW power consumption.
Keywords :
CMOS integrated circuits; cameras; liquid crystal displays; mobile handsets; peripheral interfaces; CMOS process; D-PHY chip; HS mode block; LP mode block; MIPI standard; bit rate 1 Gbit/s; camera modules; control blocks; high-speed mode block; host processor; low-power mode block; mobile devices; mobile display interface; mobile industry processor interface standard; power 0.74 mW; power consumption; size 0.13 mum; source-synchronous serial interface standard; voltage 1.2 V; Capacitance; Data communication; Inverters; Jitter; Mobile communication; Protocols; Transmitters;
Conference_Titel :
Consumer Electronics (ICCE), 2012 IEEE International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4577-0230-3
DOI :
10.1109/ICCE.2012.6162016
