• DocumentCode
    3455539
  • Title

    A model order reduction technique for nonlinear 3D interconnects using constraint variables

  • Author

    Rasekh, Ehsan ; Dounavis, Anestis

  • Author_Institution
    Univ. of Western Ontario, London, ON, Canada
  • fYear
    2011
  • fDate
    8-11 May 2011
  • Abstract
    This paper presents an efficient model order reduction algorithm for simulating large Partial Element Equivalent Circuit (PEEC) networks with many nonlinear elements. The proposed methodology is based on a multidimensional subspace method and uses constraint equations to link the nonlinear elements and biasing sources to the reduced order model. This approach significantly improves the simulation time of PEEC networks, since additional ports are not required to link the nonlinear elements to the reduced order model, yielding appreciable savings in the size of the reduced order model and computational time.
  • Keywords
    equivalent circuits; integrated circuit interconnections; PEEC network; biasing sources; constraint equation; constraint variable; model order reduction; multidimensional subspace method; nonlinear 3D interconnects; partial element equivalent circuit; Computational modeling; Equations; Integrated circuit modeling; Mathematical model; Numerical models; Reduced order systems; Solid modeling; Nonlinear systems; PEEC; analog circuits; model order reduction; numerical simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering (CCECE), 2011 24th Canadian Conference on
  • Conference_Location
    Niagara Falls, ON
  • ISSN
    0840-7789
  • Print_ISBN
    978-1-4244-9788-1
  • Electronic_ISBN
    0840-7789
  • Type

    conf

  • DOI
    10.1109/CCECE.2011.6030579
  • Filename
    6030579