Exploiting local connectivity of CMOL architecture for highly parallel orientation selective neuromorphic chips

Biological neural networks exploit local connectivity to solve complex image recognition tasks. While CMOS scaling has enabled packing more transistors and functionality into a given area, connectivity still remains an unsolved problem. The vast interconnectedness required in a neural network further exacerbates this problem. Recently memristors have emerged as viable on-chip synaptic mimics. However, the two terminal nature of these devices requires a crossbar network to enable individual addressing, in turn precluding large connectivity domain required for neural networks. In this paper, we explore the use of large fan-in locally connected spiking silicon neurons readily available in CMOL architecture to solve edge recognition in images via unsupervised learning. We show the system level simulation of an edge classifying network using Simulink employing self-inhibition and Spike Timing Dependent Plasticity. Transistor level simulation of the system blocks in Cadence Spectre is also included. We derive the constraints on nanowire length given a particular choice of memristor implementation, resulting in a maximum kernel size.