DocumentCode
3455705
Title
A Low-Cost and High Performance Pipelined Code Decompression Engine for ARM-Series Processors
Author
Jeang, Yuan-Long ; Hu, Ko-Yen
Author_Institution
Dept. of Inf. Eng., Kun Shan Univ., Tainan, Taiwan
fYear
2009
fDate
7-9 Dec. 2009
Firstpage
136
Lastpage
139
Abstract
Several techniques have been presented in our previous work for lessening the delays for instruction decompression when branching occurs. However, their costs are still relatively high. In this paper, a new preprocessing-based technique is presented to reduce the cost and increase the performance. The synthesized results for several benchmarks show that the average saving of area is about 37.5%.
Keywords
pipeline processing; reduced instruction set computing; ARM-series processors; high performance pipelined code decompression engine; instruction decompression; preprocessing-based technique; Computer aided instruction; Costs; Delay; Engines; High performance computing; Memory management; Microprocessors; Random access memory; Read only memory; Reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Computing, Information and Control (ICICIC), 2009 Fourth International Conference on
Conference_Location
Kaohsiung
Print_ISBN
978-1-4244-5543-0
Type
conf
DOI
10.1109/ICICIC.2009.25
Filename
5412308
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