Title :
A Low-Cost and High Performance Pipelined Code Decompression Engine for ARM-Series Processors
Author :
Jeang, Yuan-Long ; Hu, Ko-Yen
Author_Institution :
Dept. of Inf. Eng., Kun Shan Univ., Tainan, Taiwan
Abstract :
Several techniques have been presented in our previous work for lessening the delays for instruction decompression when branching occurs. However, their costs are still relatively high. In this paper, a new preprocessing-based technique is presented to reduce the cost and increase the performance. The synthesized results for several benchmarks show that the average saving of area is about 37.5%.
Keywords :
pipeline processing; reduced instruction set computing; ARM-series processors; high performance pipelined code decompression engine; instruction decompression; preprocessing-based technique; Computer aided instruction; Costs; Delay; Engines; High performance computing; Memory management; Microprocessors; Random access memory; Read only memory; Reduced instruction set computing;
Conference_Titel :
Innovative Computing, Information and Control (ICICIC), 2009 Fourth International Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4244-5543-0
DOI :
10.1109/ICICIC.2009.25
