CMOS pipelined A/D converters with concurrent error detection capability

This paper presents a practical implementation of the design-for-testability (DfT) technique for self-calibrated, self-corrected pipelined analog-to-digital converters (ADCs). This DfT strategy is aimed at detecting ADC malfunctions during normal operation, but since it also enhances the observability in the converter, it can facilitate off-line testing as well. A 10-b 10 MS/s converter has been chosen as a silicon demonstrator. It has been integrated in a double-poly 1.2 μm CMOS technology, using a 6-stage 3 bits per stage architecture and a fully-differential switched-capacitor (SC) implementation. The ADC operation and the feasibility of the DfT technique have been evaluated from experimental measurements