Approaching green electronics: Power efficient arithmetic in nano-scale CMOS

Manufacturers of PCs, TVs, game consoles, mobile phones, etc. are facing new demands on their products the coming decades. Such products must fulfill new requirements to be classified as green electronics. Green electronics have a wide sense regarding toxic chemicals, reuse, recycling etc. Furthermore, the energy consumption is also an important part in the perspective of the climate change and global warming. Reducing the dynamic energy consumption have for a long time been a focus for battery or cooling reasons. However, today we face new challenges; the static energy consumption is becoming dominant, in future technologies. To be able to call future electronics green, great attention must be paid on the total power consumption, not at least the static power consumption. This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown on filter architectures.