Worst case timing analysis of RISC processors: R3000/R3010 case study

Author

Hur, Yerang ; Bae, Young Hyun ; Lim, Sung-Soo ; Kim, Sung-Kwan ; Rhee, Byung-Do ; Min, Sang Lyul ; Park, Chang Yun ; Lee, Minsuk ; Shin, Heonshik ; Kim, Chong Sang

Author_Institution

Dept. of Comput. Eng., Seoul Nat. Univ., South Korea

fYear

1995

fDate

5-7 Dec 1995

Firstpage

308

Lastpage

319

Abstract

This paper presents a case study of worst case timing analysis for a RISC processor. The target machine consists of the R3000 CPU and R3010 FPA (Floating Point Accelerator). This target machine is typical of a RISC system with pipelined execution units and cache memories. Our methodology is an extension of the existing timing schema. The extended timing schema provides means to reason about the execution time variation of a program construct by surrounding program constructs due to pipelined execution and cache memories of RISC processors. The main focus of this paper is on explaining the necessary steps for performing timing analysis of a given target machine within the extended timing schema framework. This paper also gives results from experiments using a timing tool for the target machine that is built based on the extended timing schema approach

Keywords

cache storage; computer architecture; microcomputers; performance evaluation; pipeline processing; real-time systems; reduced instruction set computing; R3000 CPU; R3010 FPA; RISC processor; cache memories; extended timing schema framework; pipelined execution units; program constructs; timing analysis; worst case timing analysis; Cache memory; Computer aided software engineering; Performance analysis; Pipelines; Processor scheduling; Real time systems; Reduced instruction set computing; Scheduling algorithm; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Real-Time Systems Symposium, 1995. Proceedings., 16th IEEE

Conference_Location

Pisa

ISSN

1052-8725

Print_ISBN

0-8186-7337-0

Type

conf

DOI

10.1109/REAL.1995.495220

Filename

495220