DocumentCode
3456196
Title
Super-resolution utilizing Total Variation regularization on CELL processor
Author
Sakuta, Y. ; Tsutsui, A. ; Goto, T. ; Sakurai, M. ; Sakai, R.
Author_Institution
Dept. of Comput. Sci. & Eng., Nagoya Inst. of Technol., Nagoya, Japan
fYear
2012
fDate
13-16 Jan. 2012
Firstpage
723
Lastpage
724
Abstract
In this paper, we have proposed a new fast super-resolution magnification method utilizing the Total Variation (TV) regularization for HDTV receivers. The TV regularization approach has not been considered to be a practical technology for motion pictures because of its large computational time. We have solved this problem by applying a combination of a High-pass filter (HPF) and the simpler TV method to the TV up-sampling block in the conventional TV magnification system. The computational time has been drastically reduced by the proposed method without losing picture quality. We have implemented our system on the CELL processor, in order to examine the feasibility of SD to HD conversion in HDTV receivers. The result is successful that the computational time for one frame processing is 14.98ms, which is less than one frame time of 16.7ms.
Keywords
high definition television; high-pass filters; image resolution; microprocessor chips; television receivers; CELL processor; HDTV receivers; TV magnification system; TV regularization approach; TV up-sampling block; fast super-resolution magnification method; frame processing; high-pass filter; time 14.98 ms; time 16.7 ms; total variation regularization; HDTV; High definition video; Image edge detection; Image resolution; Interpolation; Pipelines;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2012 IEEE International Conference on
Conference_Location
Las Vegas, NV
ISSN
2158-3994
Print_ISBN
978-1-4577-0230-3
Type
conf
DOI
10.1109/ICCE.2012.6162055
Filename
6162055
Link To Document