A 12 GHz heterodyne receiver for digital video broadcasting via satellite applications in silicon bipolar technology

A single-chip 12 GHz silicon bipolar receiver for digital video broadcasting via satellite (DVB-S) applications is presented. The IC consists of a down-converter block and a PLL-based LO synthesizer. The receiver is based on a heterodyne architecture. For 12 GHz input signal it shows a con version gain of 38 dB, a single sideband noise figure of 7 dB and an output 1 dB compression point of +5 dBm. The VCO phase noise is -95 dBc/Hz at a 100 kHz offset from a 10.6 GHz carrier. The VCO tuning range is 2.2 GHz, extending from 8.6 GHz to 10.8 GHz. The current consumption of the integrated receiver is 160 mA with a 3.3 V voltage supply. This paper demonstrates the feasibility of a low-cost silicon bipolar technologies for a Ku-band DVB-S heterodyne receiver.