A novel structure of energy efficiency charge recovery logic

A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a high-speed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500 MHz to 1 GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1 GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.