Towards low frequency low noise low power body sensor network-on-chip

An application specific integrated circuit (ASIC) for body sensor network (BSN) was presented in this paper. Dedicated for low power wireless BSN-on-chip, the ASIC consists of reconfigurable analogue front-end (AFE) block, a 12-bit analogue-to-digital converter (ADC), a low power 32-bit RISC CPU ARM7TDMI, a scalable Fast Fourier Transform (FFT), a wireless power management unit (PMU) with battery charger and management, a human body channel communication (HBC) block integrated with transceiver and receiver. The ARM7TDMI, together with PMU provides flexible communication and power-control modes for improved energy efficiency. The analogue signal processing chain was designated for low frequency physiological signal acquisition. The combination of fully differential AFE and ADC offered better immunity to common-mode noise and interferences. Low power and low noise were achieved through state-of-the-art circuit design techniques. The ASIC was implemented in a standard 0.18-μm 1P6M CMOS process and the die size of the complete chip is 5 mm × 5 mm.